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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Woo Young Choi Jae Young Song Jong Duk Lee Young June Park Byung-Gook Park |
| Copyright Year | 2005 |
| Description | Author affiliation: Sch. of Electr. Eng., Seoul Nat. Univ. (Woo Young Choi; Jae Young Song; Jong Duk Lee; Young June Park; Byung-Gook Park) |
| Abstract | 70-nm I-MOS devices have been integrated with 70-nm TFETs for the first time by adopting a novel process method. The integration of the I-MOS device with the TFET is meaningful in that it compensates for weak points of each device and implements both high-performance and low-power functionality on the same substrate. Additionally, by using SOI substrate and modifying mask layout, ON/OFF current ratio of the I-MOS device is increased dramatically by a factor of more than 1000 compared with our previous works. Finally, we have investigated the applicability of the I-MOS device to inverter and 6T-SRAM cell by measurement and mixed-mode simulation. When applied to 6T-SRAM cell, CI-MOS case shows 22.6 % improvement in SNM without much penalty in cell area |
| Starting Page | 955 |
| Ending Page | 958 |
| File Size | 641310 |
| Page Count | 4 |
| File Format | |
| ISBN | 078039268X |
| DOI | 10.1109/IEDM.2005.1609519 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Tunneling FETs MOSFETs Substrates Inverters Energy consumption Voltage Leakage current Avalanche breakdown Impact ionization |
| Content Type | Text |
| Resource Type | Article |
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