NDLI: A Predictor-Based Power-Saving Policy for DRAM Memories

Content Provider	IEEE Xplore Digital Library
Author	Thomas, G. Chandrasekar, K. Akesson, B. Juurlink, B. Goossens, K.
Copyright Year	2012
Abstract	Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.
Starting Page	882
Ending Page	889
File Size	311652
Page Count	8
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory History Clocks Energy consumption Prediction algorithms Memory management Servers Power-Down Predictor-based Power Saving Policy Predictor DRAM-Memory Self-Refresh
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Power management of hybrid DRAM/PRAM-based main memory

A simulation-based study for DRAM power reduction strategies in GPGPUs

Dram decay: using decay counters to reduce energy consumption in drams abstract.

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions

DTail: a flexible approach to DRAM refresh management

Reducing Refresh Power in Mobile Devices with Morphable ECC

Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh

A Predictor-Based Power-Saving Policy for DRAM Memories

Similar Documents

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Power management of hybrid DRAM/PRAM-based main memory

A simulation-based study for DRAM power reduction strategies in GPGPUs

Dram decay: using decay counters to reduce energy consumption in drams abstract.

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions

DTail: a flexible approach to DRAM refresh management

Reducing Refresh Power in Mobile Devices with Morphable ECC

Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh

A Predictor-Based Power-Saving Policy for DRAM Memories