NDLI: Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy

Content Provider	IEEE Xplore Digital Library
Author	Latif, K. Rahmani, A.-M. Seceleanu, T. Tenhunen, H.
Copyright Year	2012
Abstract	Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5X6 crossbar is used for the proposed architecture which requires one more 5X1 multiplexer without increasing the critical path delay of the router as compared to the 5X5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.
Starting Page	34
Ending Page	41
File Size	500971
Page Count	8
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.43
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nickel Routing Fault tolerance Fault tolerant systems Power demand Network Interface (NI) Networks-on-Chip (NoC) Virtual Channel (VC) Processing Element (PE) recovery
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures

Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels

A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip

Fault-tolerant routing for on-chip network without using virtual channels

Fault-tolerant routing in A PRDT(2,1)-based NoC

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

An Enhanced Fault-Tolerant Routing Algorithm for Mesh Network-on-Chip

Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy

Similar Documents

Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures

Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels

A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip

Fault-tolerant routing for on-chip network without using virtual channels

Fault-tolerant routing in A PRDT(2,1)-based NoC

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

An Enhanced Fault-Tolerant Routing Algorithm for Mesh Network-on-Chip

Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy