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| Content Provider | IEEE Xplore Digital Library | 
|---|---|
| Author | Rutgers, J.H. Bekooij, M.J.G. Smit, G.J.M. | 
| Copyright Year | 2012 | 
| Abstract | Real-time embedded systems like smartphones tend to comprise an ever increasing number of processing cores. For scalability and the need for guaranteed performance, the use of a connection-oriented network-on-chip (NoC) is advocated. Furthermore, a distributed shared memory architecture is preferred as it simplifies software development for a multicore system. In this paper, experimental evidence is provided, showing that replacing a connection-oriented NoC by a connectionless one in a distributed shared memory system reduces the hardware costs and improves the performance. We observed that our FPGA could only support an 8-core system with a connection-oriented NoC. We exchanged the NoC with our tree-shaped, connectionless network and a ring, allowing a 32-core system in the same FPGA, mainly because of a reduced number of physical connections. Although the analytical worst-case performance slightly decreased, measurements show that the latency of latency-critical memory reads was reduced by 52% on average. | 
| Starting Page | 727 | 
| Ending Page | 730 | 
| File Size | 287834 | 
| Page Count | 4 | 
| File Format | |
| ISBN | 9781467324984 | 
| e-ISBN | 9780769547985 | 
| DOI | 10.1109/DSD.2012.54 | 
| Language | English | 
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) | 
| Publisher Date | 2012-09-05 | 
| Publisher Place | Turkey | 
| Access Restriction | Subscribed | 
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) | 
| Subject Keyword | Field programmable gate arrays Hardware Real-time systems Tiles Software Computer architecture Clocks | 
| Content Type | Text | 
| Resource Type | Article | 
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