NDLI: A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

Content Provider	IEEE Xplore Digital Library
Author	Jagtap, R. Kumar, S.S. van Leuken, R.
Copyright Year	2012
Abstract	As planar scaling to achieve higher chip integration seems to be on the brink of saturation, three-dimensional (3D) integration has emerged as a promising technology. It is critical to have efficient early stage estimation methodologies to build high performance digital systems as well as to shorten design time. In this paper, a novel methodology is proposed which takes into account key physical effects and explores Through-Silicon-Via (TSV) placement topologies for a 2-tier 3D stack. It estimates the interconnect electrical performance and TSV area penalty across two TSV performance corners. The methodology offers flexibility in selection of the CMOS technology node and the 3D stacking level. A SystemC implementation provides for parameterizability and modeling with ease and also enables integration into a high-level system simulation framework. Using our methodology, TSV placement topologies were explored for a 7-port 3D router. Our results present optimal topologies for the router for typical 45 nm and 32 nm technology nodes. They also point out unreliable topologies and give important feedback for 3D system design.
Starting Page	382
Ending Page	388
File Size	2820451
Page Count	7
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Topology Integrated circuit modeling Delay Couplings Load modeling Stacking TSV coupling 3D Stacked IC 3D-SOC 3D-SIC TSV placement methodology SystemC Keep-Out-Zone
Content Type	Text
Resource Type	Article

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