NDLI: Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration

Content Provider	IEEE Xplore Digital Library
Author	Kayaalp, M. Koc, F. Ergin, O.
Copyright Year	2012
Abstract	Today, designing reliable superscalar microprocessors is more complex and challenging than it has always been. Increasing current densities over interconnecting wires, whose dimensions are continuously scaling down, has been an important research problem. Performance and power efficiency concerns also lead to more complex structures. The complexity and the wire densities of the blocks in smaller areas make them more prone to failures and malfunctions caused by the "electromigration" problem. Most contemporary processors employ wide pipelines that are able to execute multiple instructions each cycle. Because of some limiting factors such as the dependencies and input/output latencies, pipelines are rarely used up to their full capacity, which causes some ports to be used more and worn out earlier. This paper proposes a method to help preventing chips against the corruptive effect of electromigration by distributing the utilization evenly between ports. Furthermore, in data holding structures like register files, bit level inactivity is exploited to provide further reliability improvements. This is accomplished by changing the flux density on wires through exchanging the positions of significant bits of values and changing the widths of bit line wires according to their level of usage.
Starting Page	280
Ending Page	287
File Size	1184244
Page Count	8
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.56
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Wires Program processors Pipelines Switches Current density Integrated circuit interconnections Integrated Circuit Reliability Electromigration Fault Tolerant Systems Integrated Circuit Interconnections
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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