NDLI: Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems

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Table of contents

Message from General Chair

Message from Program Chair

Program Committee

Keynotes [3 abstracts]

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip

Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS Circuits

reMORPH: A Runtime Reconfigurable Architecture

Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy

A Scalable Monitoring Infrastructure for Self-Organizing Many-Core Architectures

On the Design of Configurable Modulo 2n±1 Residue Generators

Projected Don't Cares

SUT-RNS Residue-to-Binary Converters Design

Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores

Miscellaneous Types of Partial Duplication Modifications for Availability Improvements

Reliability of Task Execution During Safe Software Processing

Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain

OWQS: One-Way Quantum Computation Simulator

The ACROSS MPSoC -- A New Generation of Multi-core Processors Designed for Safety-Critical Embedded Systems

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach

FPGA Based Real-Time Tracking Approach with Validation of Precision and Performance

Analyzing Bus Load Data Using an FPGA and a Microcontroller

On the Development of a Runtime Reconfigurable Multicore System-on-Chip

Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors

Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators

Vulnerability Analysis for Custom Instructions

A Three-Dimensional Integrated Accelerator

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF

No Principal Too Small: Memory Access Control for Fine-Grained Protection Domains

Hardware Strengthening a Distributed Logging Scheme

Trojan Immune Circuits Using Duality

Semi-distributed Control for FPGA-based Reconfigurable Systems

FPGA-based Neural Network for Nonuniformity Correction on Infrared Focal Plane Arrays

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip

Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm

ASAM: Automatic Architecture Synthesis and Application Mapping

Controlling Hardware Synthesis with Aspects

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Activity Migration in M-of-N-Systems by Means of Load-Balancing

Protecting an Asynchronous NoC against Transient Channel Faults

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration

A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-core Platforms

ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm

Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems

A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs

High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing

The Seat Adaptation System of REFLECT Project: Implementation of a Biocybernetic Loop in an Automotive Environment

The DeSyRe Project: On-Demand System Reliability

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels

COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration

Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application Program

The Influence of Implementation Technology on Dependability Parameters

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems

A Verifiable High Level Data Path Synthesis Framework

Finite State Machine Synthesis Based on Relay-Based Algorithm

VLSI Reverse Converter for RNS Based on the Moduli Set

EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off

A Dual-Core Coprocessor with Native 4D Clifford Algebra Support

SystemC Model Generation for Realistic Simulation of Networked Embedded Systems

How to Prove that a Circuit is Fault-Free?

On Modeling and Evaluation of Logic Circuits under Timing Variations

IEEE 802.11p Receiver Design for Software Defined Radio Platforms

Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios

HDCRAM Proof-of-Concept for Opportunistic Spectrum Access

A Flexible Hardware Platform for Mobile Cognitive Radio Applications

Flexible OFDM Waveform for PLC/RF In-Vehicle Communications

Open Problems in Verification and Refinement of Autonomous Robotic Systems

Cyber-Physical Systems Design for Electric Vehicles

Simulation-Based Analysis of Cyberphysical Systems

Model Checking on Hybrid Automata

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

HEAP: A Highly Efficient Adaptive Multi-processor Framework

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach

Coverage-Driven Stimuli Generation

Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory

Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins

High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band

A Virtual Platform for Performance Estimation of Many-core Implementations

Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor

A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms

Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware

A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl

Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction

Optimal 2D Data Partitioning for DMA Transfers on MPSoCs

Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures

Reducing Instruction Issue Overheads in Application-Specific Vector Processors

Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms

Adaptive Field Strength Scaling: A Power Optimization Technique for Contactless Reader / Smart Card Systems

RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion

High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC

JAAVR: Introducing the Next Generation of Security-Enabled RFID Tags

FPGA-based Design Approaches of Keccak Hash Function

PROCOMON: An Automatically Generated Predictive Control Signal Monitor

CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures

Open-People: Open Power and Energy Optimization PLatform and Estimator

A Hardware-In-the-Design Methodology for Wireless Sensor Networks Based on Event-Driven Impulse Radio Ultra-Wide Band

Energy Characterization and Classification of Embedded Operating System Services

Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE

Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation Specifications

Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis

Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC

Managing a Massively-Parallel Resource-Constrained Computing Architecture

Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core System

CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip

Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit

A Distributed Feedback Control Mechanism for Quality-of-Service Maintenance in Wireless Sensor Networks

MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC

OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters

A Game Theoretical Thermal -- Aware Run -- Time Task Synchronization Method for Multiprocessor Systems -- on -- Chip

Composable Virtual Memory for an Embedded SoC

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm

The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States

RNS Arithmetic Units for Modulo {2^n+-k}

Scalability Study of Polymorphic Register Files

Pipelined Large Multiplier Designs on FPGAs

Implementation Study of FFT on Multi-lane Vector Processors

Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs

Test Generation Approach for Post-Silicon Validation of High End Microprocessor

Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design

Scan Based Tests via Standard Interfaces

Soft Error Analysis on Communication Channels in On-Chip Communication Networks

Virtual Platform for Wireless Sensor Networks

Energy-Aware FPGA-based Architecture for Wireless Sensor Networks

Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks

A Predictor-Based Power-Saving Policy for DRAM Memories

Evaluation of an FPGA-based Reconfigurable SoC for All-Digital Flexible RF Transmitters

Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors

Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware

A Small and High-Performance Coprocessor for Fingerprint Match-on-Card

On-Package Scalability of RF and Inductive Memory Controllers

A Hardware Accelerator for Real Time Simulation of Complex Neuronal Models

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

2011 14th Euromicro Conference on Digital System Design

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

9th EUROMICRO Conference on Digital System Design (DSD'06)

8th Euromicro Conference on Digital System Design (DSD'05)

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Euromicro Symposium on Digital System Design, 2003. Proceedings.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

Proceedings Euromicro Symposium on Digital Systems Design

Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems

Content Provider	IEEE Xplore Digital Library
Author	Chagoya-Garzon, A. Rousseau, F. Petrot, F.
Copyright Year	2012
Abstract	Heterogeneous hierarchical architectures result from the interconnection of several heterogeneous MPSoCs through an efficient communication infrastructure. Each communication between two processing units requires the use of hardware devices managed by a software driver responsible to initialize, handle and complete the communication. This paper describes a multi-device driver synthesis flow based on available communication paths of the architecture. A small set of generic driver templates is available in a driver library. The flow is in charge to select one correct driver template from the library, and then to configure and specialize it in order to produce the source code. The effectiveness of our approach is illustrated by a significant example.
Starting Page	389
Ending Page	396
File Size	359746
Page Count	8
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.88
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Tiles Computer architecture Software Central Processing Unit Hierarchical systems Libraries software synthesis Communication drivers heterogeneous MPSoCs
Content Type	Text
Resource Type	Article

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