NDLI: On the Development of a Runtime Reconfigurable Multicore System-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Cazzaniga, A. Durelli, G. Pilato, C. Sciuto, D. Santambrogio, M.D.
Copyright Year	2012
Abstract	Over the last years, several research groups have built reconfigurable systems to obtain high performance at low cost by specializing the computing engine to the computation task. Nowadays, FPGA-based multi-core architectures and reconfigurable computing are widely used for embedded systems, even if the development of complete and efficient solutions on this kind of devices is still quite a complex task. Within this context, what seems to be neglected so far is the combination of a multicore architecture with reconfigurable abilities to vary at runtime not only the hardware components but also the number of the available processors. The variation of the number of processors available on the device can be performed in a dynamic way by using the proposed solution, based on a partial bitstream, characterized by the presence of a reconfigurable system in which both components and component memories can be reconfigured at run-time. This paper presents a study of the viability of making a scalable and flexible multicore System-on-Chip (MPSoC) based on customizable reconfigurable processors, called Multi-Adaptive Reconfigurable Core (MARC), providing the communication infrastructures and the memory management required to create such a complex system-on-chip.
Starting Page	132
Ending Page	135
File Size	794989
Page Count	4
File Format	PDF
ISBN	9781467324984
e-ISBN	9780769547985
DOI	10.1109/DSD.2012.93
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-05
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Runtime Hardware Motion detection System-on-a-chip Software
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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