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Dram decay: using decay counters to reduce energy consumption in drams abstract.
| Content Provider | CiteSeerX |
|---|---|
| Author | Lee, Hsien-Hsin S. Ghosh, Mrinmoy |
| Abstract | Dynamic random access memories (DRAMs) require periodic refresh for preserving data stored in them. The refresh interval for DRAMs depends on the the vendor and the design technology they use. For each refresh in a DRAM row, the stored information in each cell is read out and then written back to itself as each DRAM bit read is self-destructive. The refresh process often incurs large power and bandwidth overhead, however, it is inevitable for maintaining data correctness. This paper proposes an innovative scheme to address the energy issue in DRAMs. By using a decay counter for each memory row of a DRAM memory module, all the unnecessary periodic refresh operations can be eliminated. The basic concept behind this scheme is that a memory row that has been recently read or written to by the processor (or other devices that share the same DRAM) does not need to be refreshed again by the periodic DRAM refresh operation, thereby eliminating excessive refreshes and the energy dissipated. Based on this concept, we propose a low-cost technique in the design of the memory controller for DRAM power reduction. The simulation results show that our technique can reduce 23 % of all refresh operations. This saved 20 % of the energy consumed for refresh operations. DRAM system energy savings of up to 17 % and an average of 6% were obtained for SPEC2000 integer benchmark programs. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Dram Abstract Basic Concept Data Correctness Dram Memory Module Innovative Scheme Low-cost Technique Dram Decay Dynamic Random Access Memory Bandwidth Overhead Dram Bit Spec2000 Integer Benchmark Program Dram System Energy Saving Dram Row Energy Issue Decay Counter Dram Power Reduction Refresh Process Refresh Operation Memory Controller Memory Row Reduce Energy Consumption Stored Information Unnecessary Periodic Refresh Operation Using Decay Counter Large Power Simulation Result Periodic Dram Refresh Operation Refresh Interval Periodic Refresh Excessive Refreshes Design Technology |
| Content Type | Text |
| Resource Type | Article |
