NDLI: Semi-automation of Configuration Files Generation for Heterogeneous Multi-tile Systems

Content Provider	IEEE Xplore Digital Library
Author	Chagoya-Garzon, A. Poste, N. Rousseau, F.
Copyright Year	2011
Abstract	Heterogeneous Multi-Processor System-on-Chips (HMPSoCs) offer an attractive alternative to homogeneous systems to achieve the increasing requirements of modern media-processing applications. Such systems take advantage of the heterogeneity of their processing units (RISC vs. VLIW) combined with efficient memory architecture and a specific communication infrastructure. However, the complexity of such architectures requires efficient programming tools. They rely on software generation flows that have already been widely studied. Connecting several HMPSoCs to form a heterogeneous system is one solution to target the highly demanding applications belonging to the high performance-computing world. Binary code generation for such many-processor architectures faces new challenges. Indeed, binary generation requires a back-end part composed of processor-specific tools like compilers or linkers, that can no longer be configured by hand when dealing with hundreds of processors. We address in this paper the need to automate the whole configuration process of binary generation flows through the study of two important configuration aspects: the memory mapping and communication configurations. We propose a prototype including a semi-automatic configuration generation module that has been successfully applied on a particularly complex application (LQCD).
Starting Page	157
Ending Page	166
File Size	643891
Page Count	10
File Format	PDF
ISBN	9781457705441
ISSN	07303157
e-ISBN	9780769544397
DOI	10.1109/COMPSAC.2011.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Hardware Reduced instruction set computing Tiles System-on-a-chip low-level software configuration files heterogeneous multi-processor architecture
Content Type	Text
Resource Type	Article
Subject	Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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