NDLI: When to stop verification?: Statistical trade-off between expected loss and simulation cost

Content Provider	IEEE Xplore Digital Library
Author	Jha, S.K. Langmead, C.J. Mohalik, S. Ramesh, S.
Copyright Year	2011
Description	Author affiliation: Computer Science Department and Lane Center for Computational Biology, Carnegie Mellon University (Langmead, C.J.) \|\| India Science Lab, General Motors Research and Development, Bangalore, India (Mohalik, S.; Ramesh, S.) \|\| Computer Science Department, University of Central Florida, Orlando, Florida (Jha, S.K.)
Abstract	Exhaustive state space exploration based verification of embedded system designs remains a challenge despite three decades of active research into Model Checking. On the other hand, simulation based verification of even critical embedded system designs is often subject to financial budget considerations in practice. In this paper, we suggest an algorithm that minimizes the overall cost of producing an embedded system including the cost of testing the embedded system and expected losses from an incompletely tested design. We seek to quantify the trade-off between the budget for testing and the potential financial loss from an incorrect design. We demonstrate that our algorithm needs only a logarithmic number of test samples in the cost of the potential loss from an incorrect validation result. We also show that our approach remains sound when only upper bounds on the potential loss and lower bounds on the cost of simulation are available. We present experimental evidence to corroborate our theoretical results.
Starting Page	1
Ending Page	6
File Size	131600
Page Count	6
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Biological system modeling Computational modeling Stochastic processes Embedded systems Bayesian methods Adaptation model Probabilistic logic
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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