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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stattelmann, S. Bringmann, O. Rosenstiel, W. |
| Copyright Year | 2011 |
| Description | Author affiliation: FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, D-76131 Karlsruhe, Germany (Stattelmann, S.; Bringmann, O.) || University of Tuebingen, Sand 13, D-72076 Tuebingen, Germany (Rosenstiel, W.) |
| Abstract | This work presents a SystemC-based simulation approach for fast performance analysis of parallel software components, using source code annotated with low-level timing properties. In contrast to other source-level approaches for performance analysis, timing attributes obtained from binary code can be annotated even if compiler optimizations are used without requiring changes in the compiler. To consider concurrent accesses to shared resources like caches accurately during a source-level simulation, an extension of the SystemC TLM-2.0 standard for reducing the necessary synchronization overhead is proposed as well. This enables the simulation of low-level timing effects without performing a full-fledged instruction set simulation and at speeds close to pure native execution. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 335225 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612842080 |
| ISSN | 15301591 |
| e-ISBN | 9783981080186 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-03-14 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Synchronization Binary codes Analytical models Kernel Predictive models Software performance System analysis and design Timing Modeling |
| Content Type | Text |
| Resource Type | Article |
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