NDLI: Error prediction based on concurrent self-test and reduced slack time

Content Provider	IEEE Xplore Digital Library
Author	Gherman, V. Massas, J. Evain, S. Chevobbe, S. Bonhomme, Y.
Copyright Year	2011
Description	Author affiliation: CEA, LIST, Embedded Systems Reliability Laboratory, Point Courrier 94, 91191 Gif-sur-Yvette CEDEX, France (Gherman, V.; Massas, J.; Evain, S.; Chevobbe, S.; Bonhomme, Y.)
Abstract	Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency. Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent self-test of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.
Starting Page	1
Ending Page	6
File Size	165055
Page Count	6
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Pipelines Flip-flops Delay Circuit faults Aging Clocks Built-in self-test
Content Type	Text
Resource Type	Article

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