NDLI: Efficient validation input generation in RTL by hybridized source code analysis

Content Provider	IEEE Xplore Digital Library
Author	Lingyi Liu Vasudevan, S.
Copyright Year	2011
Description	Author affiliation: Department of ECE, University of Illinois at Urbana-Champaign, Urbana, IL, USA (Lingyi Liu; Vasudevan, S.)
Abstract	We present HYBRO, an automatic methodology to generate high coverage input vectors for Register Transfer Level (RTL) designs based on branch-coverage directed approach. HYBRO uses dynamic simulation data and static analysis of RTL control flow graphs (CFGs). A concrete simulation is applied over a fixed number of cycles. Instrumented code records the branches covered. The corresponding symbolic trace is extracted from the CFG with an RTL symbolic execution engine. A guard in the symbolic expression is mutated. If the mutated guard has dependent branches that have not already been covered, it is mutated and passed to an SMT solver. A satisfiable assignment generates a valid input vector. We implement the Verilog RTL symbolic execution engine and show that the notion of branch-coverage directed exploration can avoid path explosion caused by previous path-based approach to input vector generation and achieve full branch and more than 90% functional(assertion) coverage quickly on ITC99 benchmark and several Openrisc designs. We also describe two types of optimizations a) dynamic UD chain slicing b)local conflict resolution to speed up HYBRO by 1.6–12 times on different benchmarks.
Starting Page	1
Ending Page	6
File Size	128175
Page Count	6
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Concrete Instruments Engines Optimization Hardware design languages Registers Measurement
Content Type	Text
Resource Type	Article

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