NDLI: Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Content Provider	IEEE Xplore Digital Library
Author	Indrusiak, L.S. dos Santos, O.M.
Copyright Year	2011
Description	Author affiliation: Real-Time Systems Group, Department of Computer Science, University of York, York, United Kingdom (Indrusiak, L.S.; dos Santos, O.M.)
Abstract	Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.
Starting Page	1
Ending Page	6
File Size	159376
Page Count	6
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Time domain analysis Time varying systems Interference Accuracy Jitter System-on-a-chip Payloads simulation system specification transaction-level modeling network-on-chip on-chip multiprocessing
Content Type	Text
Resource Type	Article

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