NDLI: NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

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Table of contents

Biologically-inspired massively-parallel architectures — Computing beyond a million processors

VESPA: Variability emulation for System-on-Chip performance analysis

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization

An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems

Register allocation for simultaneous reduction of energy and peak temperature on registers

A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels

Fast statistical analysis of RC nets subject to manufacturing variabilities

A scaled random walk solver for fast power grid analysis

A block-diagonal structured model reduction scheme for power grid networks

Logic synthesis and physical design: Quo vadis?

Panel and embedded tutorial — Logic synthesis and place and route: After 20 years of engagement, wedding in view?

Time redundant parity for low-cost transient error detection

Cross-layer optimized placement and routing for FPGA soft error mitigation

Trigonometric method to handle realistic error probabilities in logic circuits

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

FlexRay switch scheduling — A networking concept for electric vehicles

A reconfiguration approach for fault-tolerant FlexRay networks

Simplified programming of faulty sensor networks via code transformation and run-time interval computation

Parallel accelerators for GlimmerHMM bioinformatics algorithm

An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms

Sub-clock power-gating technique for minimising leakage power during active mode

An automated data structure migration concept — From CAN to Ethernet/IP in automotive embedded systems (CANoverIP)

Formal specification and systematic model-driven testing of embedded automotive systems

Embedded tutorial: Addressing critical power management verification issues in low power designs

Topologically homogeneous power-performance heterogeneous multicore systems

Variability-aware duty cycle scheduling in long running embedded sensing systems

Reliability-aware thermal management for hard real-time applications on multi-core processors

Clause simplification through dominator analysis

Integration of orthogonal QBF solving techniques

STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra

Empirical design bugs prediction for verification

Decision ordering based property decomposition for functional test generation

Towards coverage closure: Using GoldMine assertions for generating design validation stimulus

Scalable hybrid verification for embedded software

Diagnosing scan chain timing faults through statistical feature analysis of scan images

Design-for-test methodology for non-scan at-speed testing

A clock-gating based capture power droop reduction methodology for at-speed scan testing

Pruning infeasible paths for tight WCRT analysis of synchronous programs

Fast and accurate resource conflict simulation for performance analysis of multi-core systems

An approach to improve accuracy of source-level TLMs of embedded software

Host-compiled multicore RTOS simulator for embedded real-time software development

A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

A low-power VLIW processor for 3GPP-LTE complex numbers processing

Architecture and FPGA-implementation of a high throughput $K^{+}-Best$ detector

An energy-efficient 64-QAM MIMO detector for emerging wireless standards

Beyond UPF & CPF: Low-power design and verification

Enabling improved power management in multicore processors through clustered DVFS

Dynamic thermal management in 3D multi-core architecture through run-time adaptation

Distributed hardware matcher framework for SoC survivability

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

Interpolation sequences revisited

Automated debugging of SystemVerilog assertions

Counterexample-guided SMT-driven optimal buffer sizing

DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling

Cycle-count-accurate processor modeling for fast and accurate system-level simulation

A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems

Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

A true power detector for RF PA built-in calibration and testing

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Testing of high-speed DACs using PRBS generation with “Alternate-Bit-Tapping”

Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations

Design space exploration for 3D-stacked DRAMs

Analytical heat transfer model for thermal through-silicon vias

A new architecture for power network in 3D IC

Achieving composability in NoC-based MPSoCs through QoS management at software level

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links

Guaranteed service virtual channel allocation in NoCs for run-time task scheduling

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

Entering the path towards terabit/s wireless links

Smart imagers of the future

Power-driven global routing for multi-supply voltage domains

Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance

Steiner tree based rotary clock routing with bounded skew and capacitive load balancing

On routing fixed escaped boundary pins for high speed boards

Dynamic write limited minimum operating voltage for nanoscale SRAMs

Variation aware dynamic power management for chip multiprocessor architectures

Leakage aware energy minimization for real-time systems under the maximum temperature constraint

Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks

Developing an integrated verification and debug methodology

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations

Power management verification experiences in Wireless SoCs

Challenges in designing high speed memory subsystem for mobile applications

Solid state photodetectors for nuclear medical imaging applications

Fault grading of software-based self-test procedures for dependable automotive applications

CARAT: Context-aware runtime adaptive task migration for multi core architectures

A rule-based static dataflow clustering algorithm for efficient embedded software synthesis

Demand code paging for NAND flash in MMU-less embedded systems

Architectures for online error detection and recovery in multicore processors

Low-power smart industrial control

Low power interconnects for SIMD computers

Wireless innovations for smartphones

Flow-based partitioning and position constraints in VLSI placement

Integrated circuit white space redistribution for temperature optimization

Timing-constrained I/O buffer placement for flip-chip designs

Floorplanning exploration and performance evaluation of a new Network-on-Chip

Worst-case temperature analysis for real-time systems

Black-box leakage power modeling for cell library and SRAM compiler

Clock gating optimization with delay-matching

A low complexity stopping criterion for reducing power consumption in turbo decoders

A novel tag access scheme for low power L2 cache

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

ReliNoC: A reliable network for priority-based on-chip communication

FARM: Fault-aware resource management in NoC-based multiprocessor platforms

On diagnosis of multiple faults using compacted responses

On multiplexed signal tracing for post-silicon debug

Eliminating data invalidation in debugging multiple-clock chips

Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems

Gemma in April: A matrix-like parallel programming architecture on OpenCL

Evaluating the potential of graphics processors for high performance embedded computing

Virtual Manycore platforms: Moving towards 100+ processor cores

Embedded software debug and test: Needs and requirements for innovations in debugging

Powering and communicating with mm-size implants

An antenna-filter codesign for cardiac implants

Design implications of memristor-based RRAM cross-point structures

Robust 6T Si tunneling transistor SRAM design

Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs

Controlled timing-error acceptance for low energy IDCT design

Energy parsimonious circuit design through probabilistic pruning

Stage number optimization for switched capacitor power converters in micro-scale energy harvesting

Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring

VANDAL: A tool for the design specification of nanophotonic networks

Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits

On design of test structures for lithographic process corner identification

An electrical test method for MEMS convective accelerometers: Development and evaluation

Correlating inline data with final test outcomes in analog/RF devices

Systematic design of a programmable low-noise CMOS neural interface for cell activity recording

A real-time compressed sensing-based personal electrocardiogram monitoring system

A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores

An effective multi-source energy harvester for low power applications

Composing heterogeneous components for system-wide performance analysis

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools

Architectures and modeling of predictable memory controllers for improved system integration

SoC infrastructures for predictable system integration

Smart devices panel session — Integrating the real world interfaces

Re-engineering cyber-physical control applications for hybrid communication protocols

Precise WCET calculation in highly variant real-time systems

Optimal scheduling of switched FlexRay networks

On the efficacy of NBTI mitigation techniques

Partitioned cache architectures for reduced NBTI-induced aging

Adaptive voltage over-scaling for resilient applications

Design of voltage-scalable meta-functions for approximate computing

MLP aware heterogeneous memory system

Impact of process variation on endurance algorithms for wear-prone memories

Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Scratchpad memory optimizations for digital signal processing applications

Robustness analysis of 6T SRAMs in memory retention mode under PVT variations

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation

Proactive recovery for BTI in high-k SRAM cells

The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1

Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques

LOEDAR: A low cost error detection and recovery scheme for ECC

Low-cost fault detection method for ECC using Montgomery powering ladder

Methods and tools for component-based system design

Using contract-based component specifications for virtual integration testing and architecture design

Component-based design for the future

Sensor networks on the car: State of the art and future challenges

Real-time wireless communication in automotive applications

Wireless communication and energy harvesting in automobiles

Power management trends in portable consumer applications

An efficient mask optimization method based on homotopy continuation technique

Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips

High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface

Verifying dynamic aspects of UML models

Automated construction of fast and accurate system-level models for wireless sensor networks

Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

A high-level analytical model for application specific CMP design exploration

Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model

A method for fast jitter tolerance analysis of high-speed PLLs

SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs

Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects

Energy analysis methods and tools for modelling and Optimizing monitoring tyre systems

System level techniques to improve reliability in high power microcontrollers for automotive applications

System-level power estimation methodology using cycle- and bit-accurate TLM

Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems

A workflow for runtime adaptive task allocation on heterogeneous MPSoCs

Energy-efficient scheduling of real-time tasks on cluster-based multicores

E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories

Modeling manufacturing process variation for design and test

Variability aware modeling for yield enhancement of SRAM and logic

Correlating models and silicon for improved parametric yield

Understanding the role of buildings in a smart microgrid

Smart systems at ST

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs

SHARC: A streaming model for FPGA accelerators and its application to Saliency

A reconfigurable, pipelined, conflict directed jumping search SAT solver

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication

Frugal but flexible multicore topologies in support of resource variation-driven adaptivity

Minority-Game-based resource allocation for run-time reconfigurable multi-core processors

Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique

Simulation based tuning of system specification

An extension to SystemC-A to support mixed-technology systems with distributed components

Stochastic circuit reliability analysis

As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization

Built-in generation of functional broadside tests

SAT-based fault coverage evaluation in the presence of unknown values

When to stop verification?: Statistical trade-off between expected loss and simulation cost

Resynchronization of Cyclo-Static Dataflow graphs

Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints

3D Embedded multi-core: Some perspectives

A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC

State of the art verification methodologies in 2015

Energy-modulated computing

$I^{2}CRF:$ Incremental interconnect customization for embedded reconfigurable fabrics

MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers

Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor

An efficient algorithm for multi-domain clock skew scheduling

A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication

Redressing timing issues for speed-independent circuits in deep submicron age

Realistic performance-constrained pipelining in high-level synthesis

Optimisation of mutually exclusive arithmetic sum-of-products

Intermediate representations for controllers in chip generators

Power optimization in heterogenous datapaths

Abstract state machines as an intermediate representation for high-level synthesis

Design automation for IEEE P1687

On testing prebond dies with incomplete clock networks in a 3D IC using DLLs

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing

Adaptive test optimization through real time learning of test effectiveness

A high-performance parallel implementation of the Chambolle algorithm

Depth-directed hardware object detection

Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding

An integrated platform for advanced diagnostics

X-SENSE: Sensing in extreme environments

Towards thermally-aware design of 3D MPSoCs with inter-tier cooling

A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation

Statistical aspects of NBTI/PBTI and impact on SRAM yield

Mathematical approach based on a “Design of Experiment” to simulate process variations

System-assisted analog mixed-signal design

Panel: What does the power industry need from the EDA industry and what is the EDA industry doing about it?

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Loop distribution for K-loops on Reconfigurable Architectures

mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions

Reliability-driven don't care assignment for logic synthesis

A new circuit simplification method for error tolerant applications

Aging-aware timing analysis and optimization considering path sensitization

Efficient parameter variation sampling for architecture simulations

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models

A unified methodology for pre-silicon verification and post-silicon validation

Efficient validation input generation in RTL by hybridized source code analysis

An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation

A confidence-driven model for error-resilient computing

Eliminating speed penalty in ECC protected memories

Error correcting code analysis for cache memory high reliability and performance

Error prediction based on concurrent self-test and reduced slack time

Physically unclonable functions for embeded security based on lithographic variation

RON: An on-chip ring oscillator network for hardware Trojan detection

Arithmetic logic units with high error detection rates to counteract fault attacks

Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers

Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?

Automated constraint-driven topology synthesis for analog circuits

A new method for automated generation of compensation networks — The EDA Designer Finger

Strategies for initial sizing and operating point analysis of analog circuits

Generator based approach for analog circuit and layout design and optimization

Buffering implications for the design space of streaming MEMS storage

Efficient RC power grid verification using node elimination

A novel TSV topology for many-tier 3D power-delivery networks

Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories

DynOAA — Dynamic offset adaptation algorithm for improving response times of CAN systems

A sensor fusion algorithm for an integrated angular position estimation with inertial measurement units

Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation

System-level energy-efficient scheduling for hard real-time embedded systems

Timing error statistics for energy-efficient robust DSP systems

ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications

An energy-efficient 3D CMP design with fine-grained voltage scaling

Optimized model checking of multiple properties

A new distributed event-driven gate-level HDL simulation by accurate prediction

Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system

A 3D reconfigurable platform for 4G telecom applications

An LOCV-based static timing analysis considering spatial correlations of power supply variations

Compiling SyncCharts to Synchronous C

Optimization of stateful hardware acceleration in hybrid architectures

Formal reset recovery slack calculation at the register transfer level

Multi-granularity thermal evaluation of 3D MPSoC architectures

Two methods for 24 Gbps test signal synthesis

3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers

Architectural exploration of 3D FPGAs towards a better balance between area and delay

NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

Early chip planning cockpit

Power reduction via near-optimal library-based cell-size selection

Scalable packet classification via GPU metaprogramming

Battery-supercapacitor hybrid system for high-rate pulsed load applications

Feedback based droop mitigation

A 0.964mW digital hearing aid system

HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiency

Fine-grain OpenMP runtime support with explicit communication hardware primitives

Transition-Time-Relation based capture-safety checking for at-speed scan test generation

2D and 3D integration with organic and silicon electronics

Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes

A fault-tolerant deadlock-free adaptive routing for on chip interconnects

Evaluating energy consumption of homogeneous MPSoCs using spare tiles

Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC

Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown

Multi-level attacks: An emerging security concern for cryptographic hardware

A new reversible design of BCD adder

jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip

Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching

A multi-objective decision-theoretic exploration algorithm for platform-based design

Predicting bus contention effects on energy and performance in multi-processor SoCs

A specialized low-cost vectorized loop buffer for embedded processors

Determining the minimal number of lines for large reversible circuits

Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation

A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features

Coordinate strip-mining and kernel fusion to lower power consumption on GPU

An efficient Quantum-Dot Cellular Automata adder

Priority division: A high-speed shared-memory bus arbitration with bounded latency

System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks

A UML 2-based hardware-software co-design framework for body sensor network applications

An area-efficient multi-level single-track pipeline template

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays

Timing variation-aware custom instruction extension technique

Pseudo circuit model for representing uncertainty in waveforms

A global postsynthesis optimization method for combinational circuits

An algorithm to improve accuracy of criticality in statistical static timing analysis

An approach for dynamic selection of synthesis transformations based on Markov Decision Processes

Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis

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NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs

Content Provider	IEEE Xplore Digital Library
Author	Porquet, J. Greiner, A. Schwarz, C.
Copyright Year	2011
Description	Author affiliation: LIP6 Laboratory, Université Pierre et Marie Curie (Porquet, J.; Greiner, A.) \|\| Nagravision (Schwarz, C.)
Abstract	For many embedded systems, data protection is becoming a major issue. On those systems, processors are often heterogeneous and prevent from deploying a common, trusted hypervisor on all of them. Multiple native software stacks are thus bound to share the resources without protection between them. NoC-MPU is a Memory Protection Unit allowing to support the secure and flexible co-hosting of multiple native software stacks running in multiple protection domains, on any shared memory MP-SoC using a NoC. This paper presents a complete hardware architecture of this NoC-MPU mechanism, along with a software trusted model organization.
Starting Page	1
Ending Page	4
File Size	86420
Page Count	4
File Format	PDF
ISBN	9781612842080
ISSN	15301591
e-ISBN	9783981080186
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-03-14
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Permission Program processors Hardware Computer architecture Protocols
Content Type	Text
Resource Type	Article

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