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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jae-Seok Yang Athikulwongse, K. Young-Joon Lee Sung Kyu Lim Pan, D.Z. |
| Copyright Year | 2010 |
| Description | Author affiliation: School of ECE, Georgia Institute of Technology, Atlanta, Georgia, USA (Athikulwongse, K.; Young-Joon Lee; Sung Kyu Lim) || Department of ECE, University of Texas at Austin, Austin, TX USA (Jae-Seok Yang; Pan, D.Z.) |
| Abstract | As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and silicon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile stress on silicon near TSV. In this paper, we propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, we generate a stress contour map with an analytical radial stress model. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relation between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. It is interesting to observe that rise and fall time react differently to stress and relative locations with respect to TSVs. Overall, TSV stress induced timing variations can be as much as ± 10% for an individual cell. Thus as an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. |
| Starting Page | 803 |
| Ending Page | 806 |
| File Size | 564155 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Through-silicon vias Timing Three-dimensional integrated circuits Tensile stress Silicon Thermal stresses Delay Geometry Stacking Thermal expansion timing analysis 3DIC TSV stress mobility variation |
| Content Type | Text |
| Resource Type | Article |
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