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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Beece, D.K. Jinjun Xiong Visweswariah, C. Zolotov, V. Yifang Liu |
| Copyright Year | 2010 |
| Description | Author affiliation: Texas A & M University College Station, TX (Yifang Liu) || IBM Thomas J. Watson Research Center Yorktown Heights, NY (Beece, D.K.; Jinjun Xiong; Visweswariah, C.; Zolotov, V.) |
| Abstract | Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing problem warrants revisiting. This paper addresses the sizing problem statistically in which transistor sizes are automatically adjusted to maximize parametric yield at a given timing performance, or maximize performance at a required parametric yield. Specifically, we describe an implementation of a statistical tuner using interior point nonlinear optimization with an objective function that is directly dependent on statistical process variation. Our results show that for process variation sensitive circuits, consisting of thousands of independently tunable devices, a statistically aware tuner can give more robust, higher yield solutions when compared to deterministic circuit tuning and is thus an attractive alternative to the Monte Carlo methods that are typically used to size devices in such circuits. To the best of our knowledge, this is the first publication of a working system to optimize device sizes in custom circuits using a process variation aware tuner. |
| Starting Page | 781 |
| Ending Page | 786 |
| File Size | 363551 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Digital circuits Timing Circuit testing Tuners Circuit optimization Tuned circuits Delay Circuit simulation Time domain analysis Integrated circuit modeling Custom Circuits Optimization |
| Content Type | Text |
| Resource Type | Article |
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