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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Horowitz, M. Jeeradit, M. Lau, F. Liao, S. ByongChan Lim Mao, J. |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Electrical Engineering, Stanford University, Stanford, CA, USA (Horowitz, M.; Jeeradit, M.; Lau, F.; Liao, S.; ByongChan Lim; Mao, J.) |
| Abstract | As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model. |
| Starting Page | 425 |
| Ending Page | 430 |
| File Size | 320494 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Analog circuits Circuit simulation Digital circuits Hardware design languages Circuit testing Voltage Signal design Design automation Linear systems Digital systems model-first design Analog validation design methodology equivalence checking fault coverage formal validation |
| Content Type | Text |
| Resource Type | Article |
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