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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tak-Yung Kim Taewhan Kim |
| Copyright Year | 2010 |
| Description | Author affiliation: School of Electrical Engineering and Computer Science Seoul National University, Korea (Tak-Yung Kim; Taewhan Kim) |
| Abstract | This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the pre-bond testability by allocating specially designed resources called TSV-buffers and redundant trees with transmission gates. We proposes viable solutions to the two fundamental problems of the previous work: (1) using much less buffer resources by preventing (potentially ‘bad’) TSV-buffers with a new tree topology generation algorithm; (2) completely removing the transmission gate control lines by using a specially designed component called self controlled clock transmission gate (SCCTG). Compared to the existing 3D tree topology generation algorithms, solution 1 can use 56%–88% less number of TSVs, 53%–67% less number of buffers, 22%–65% less total wirelength, and 26%–43% less clock power for the benchmark circuits with dense sink placements. Moreover, solution 2 reduces the total wirelength of all the benchmark circuits by 17% and 23% on average for the 2-die and 4-die stacked 3D ICs, respectively. |
| Starting Page | 723 |
| Ending Page | 728 |
| File Size | 494108 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Clocks Integrated circuit testing Integrated circuit synthesis Signal synthesis Three-dimensional integrated circuits Stacking Resource management Algorithm design and analysis Circuit topology Power generation buffer insertion 3D ICs clock tree optimization routing |
| Content Type | Text |
| Resource Type | Article |
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