NDLI: Rewiring for robustness

Content Provider	IEEE Xplore Digital Library
Author	Jose, M. Yu Hu Majumdar, R. Lei He
Copyright Year	2010
Description	Author affiliation: Electrical and Computer Engineering Department, University of Alberta (Yu Hu) \|\| Computer Science Department, University of California, Los Angeles (Jose, M.; Majumdar, R.) \|\| Electrical Engineering Department, University of California, Los Angeles (Lei He)
Abstract	Logic synthesis for soft error mitigation is increasingly important in a wide range of applications of FPGAs. We present R2, an algorithm for rewiring a post-layout LUT-based circuit that reduces the overall criticality of the circuit, where criticality is the fraction of primary inputs that lead to observable errors at the primary outputs if an single event upset inverts a configuration bit. Our algorithm explicitly optimizes the robustness of the interconnect, the dominant component of FPGAs. The key idea of R2 is to exploit Boolean flexibilities in the circuit implementation to replace wires with high criticality with those with lower criticality while preserving the circuit functionality. We estimate criticalities using a Monte Carlo fault simulation. We represent flexibilities using SPFDs (Set of Pairs of Functions to be Distinguished), and use criticality information to choose candidates for rewiring, assigning the maximum flexibility to high criticality wires. Compared to IPR, a recent robust logic optimization, our implementation increases MTTF (Mean Time to Failure) by 24%, showing for the first time, the advantages of exploiting Boolean flexibilities in optimizing for robustness. In addition, R2 achieves 5% and 2% more reduction on the number of wires and LUTs in an FPGA than that obtained by the existing rewiring algorithm for area minimization.
Starting Page	469
Ending Page	474
File Size	253107
Page Count	6
File Format	PDF
ISBN	9781424466771
ISSN	0738100X
e-ISBN	9781450300025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Robustness Field programmable gate arrays Wires Flexible printed circuits Logic Circuit synthesis Single event upset Integrated circuit interconnections Monte Carlo methods Circuit faults Soft Errors SPFD FPGA Rewiring Logic synthesis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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