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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bansal, S. Rey, J.C. Yang, A. Myung-Soo Jang Lu, L.C. Magarshack, P. Pol, M. Radojcic, R. |
| Copyright Year | 2010 |
| Description | Author affiliation: Taiwan Semiconductor Manufacturing Co., Hsinchu, Taiwan R.O.C (Lu, L.C.) || Qualcomm, San Diego, CA, USA (Radojcic, R.) || Mentor Graphics San Jose, California, USA (Rey, J.C.) || Samsung Electronics, Yongin-City, Gyeonggi-Do, Korea (Myung-Soo Jang) || IMEC, Leuven, Belgium (Pol, M.) || Cadence, San Jose, California, USA (Bansal, S.) || Apache Design Solutions San Jose, CA, USA (Yang, A.) || ST Microelectronics Crolles, Cedex, France (Magarshack, P.) |
| Abstract | The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and "How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain "Are we there yet?" "Is it now or the future?" |
| Starting Page | 298 |
| Ending Page | 299 |
| File Size | 157451 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Through-silicon vias Integrated circuit interconnections Three-dimensional integrated circuits Electronic design automation and methodology Integrated circuit packaging Integrated circuit technology Design methodology Silicon CMOS technology Stacking integrated circuits 3-D |
| Content Type | Text |
| Resource Type | Article |
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