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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xin-Wei Shih Yao-Wen Chang |
| Copyright Year | 2010 |
| Description | Author affiliation: Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan (Xin-Wei Shih; Yao-Wen Chang) |
| Abstract | In high-performance synchronous chip design, a buffered clock tree with small clock skew is essential for improving clocking speed. Due to the insufficient accuracy of timing models for modern chip design, embedding simulation into a clock-tree synthesis flow becomes inevitable. Consequently, the runtime for clock-tree synthesis becomes prohibitively huge as the complexity of chip designs grows rapidly. To construct a buffered clock tree efficiently, we propose an ultra fast timing-model independent approach to perform skew minimization by structure optimization. To achieve the goal, a novel clock-tree structure, called symmetrical structure, is presented. At each level of a symmetrical clock tree, the number of branches, the wire-length, and the inserted buffers are almost the same. It is natural that the clock skew could be minimized if the configurations of all paths from the clock source to sinks are similar. By symmetrically constructing a clock tree, the clock skew can be minimized without referring to simulation information. Experimental results show that our approach can not only efficiently construct a buffered clock tree, but also effectively minimize clock skew with marginal wiring overheads. Based on a set of commonly used IBM benchmarks, for example, a state-of-the-art work without (with) ngspice simulation results in averagely 7.93X (2.77X) clock skew and requires 46X (24343X) runtime over our approach. |
| Starting Page | 80 |
| Ending Page | 85 |
| File Size | 455754 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424466771 |
| ISSN | 0738100X |
| e-ISBN | 9781450300025 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Clocks Chip scale packaging Timing Wiring Delay Minimization Accuracy Runtime Design engineering Computational modeling |
| Content Type | Text |
| Resource Type | Article |
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