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Content Provider | IEEE Xplore Digital Library |
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Author | Chan, J. Parameswaran, S. |
Copyright Year | 2008 |
Description | Author affiliation: Univ. of New South Wales, Sydney (Chan, J.; Parameswaran, S.) |
Abstract | Networks-on-chip (NoC) have been widely proposed as the future communication paradigm for use in next-generation system-on-chip. In this paper, we present NoCOUT, a methodology for generating an energy optimized application specific NoC topology which supports both point-to-point and packet-switched networks. The algorithm uses a prohibitive greedy iterative improvement strategy to explore the design space efficiently. A system-level floorplanner is used to evaluate the iterative design improvements and provide feedback on the effects of the topology on wire length. The algorithm is integrated within a NoC synthesis framework with characterized NoC power and area models to allow accurate exploration for a NoC router library. We apply the topology generation algorithm to several test cases including real-world and synthetic communication graphs with both regular and irregular traffic patterns, and varying core sizes. Since the method is iterative, it is possible to start with a known design to search for improvements. Experimental results show that many different applications benefit from a mix of ";on chip networks"; and ";point-to-point networks";. With such a hybrid network, we achieve approximately 25% lower energy consumption (with a maximum of 37%) than a state of the art min-cut partition based topology generator for a variety of benchmarks. In addition, the average hop count is reduced by 0.75 hops, which would significantly reduce the network latency. |
Starting Page | 265 |
Ending Page | 270 |
File Size | 164605 |
Page Count | 6 |
File Format | |
ISBN | 9781424419210 |
DOI | 10.1109/ASPDAC.2008.4483953 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2008-03-21 |
Publisher Place | South Korea |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Network-on-a-chip Network topology Iterative algorithms Space exploration Next generation networking System-on-a-chip Optimization methods Algorithm design and analysis Feedback Wire |
Content Type | Text |
Resource Type | Article |
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