NDLI: Low power clock buffer planning methodology in F-D placement for large scale circuit design

Content Provider	IEEE Xplore Digital Library
Author	Yanfeng Wang Qiang Zhou Yici Cai Jiang Hu Xianlong Hong Jinian Bian
Copyright Year	2008
Description	Author affiliation: Tsinghua Univ., Beijing (Yanfeng Wang; Qiang Zhou; Yici Cai)
Abstract	Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buffers for robustness against variations. That is, clock buffers are often placed far from ideal locations to avoid overlap with logic cells. As a result, both power dissipation and timing are degraded. In order to solve this problem, we propose a low power clock buffer planning methodology which is integrated with cell placement. A Bin- Divided Grouping algorithm is developed to construct virtual buffer tree, which can explicitly model the clock buffers in placement. The virtual buffer tree is dynamically updated during the placement to reflect the changes of latch locations. To reduce power dissipation, latch clumping is incorporated with the clock buffer planning. The experimental results show that our method can reduce clock power significantly by 21% on average.
Starting Page	370
Ending Page	375
File Size	311917
Page Count	6
File Format	PDF
ISBN	9781424419210
DOI	10.1109/ASPDAC.2008.4483977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-21
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Large-scale systems Circuit synthesis Power dissipation Timing Delay Merging Logic Degradation Latches
Content Type	Text
Resource Type	Article

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