NDLI: A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

Content Provider	IEEE Xplore Digital Library
Author	Fei Wang Yu Hu Huawei Li Xiaowei Li
Copyright Year	2008
Description	Author affiliation: Inst. of Comput. Technol. Chinese Acad. of Sci., Beijing (Fei Wang; Yu Hu; Huawei Li; Xiaowei Li)
Abstract	The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.
Starting Page	571
Ending Page	576
File Size	168388
Page Count	6
File Format	PDF
ISBN	9781424419210
DOI	10.1109/ASPDAC.2008.4484017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-21
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Combinational circuits Fault diagnosis Design for disassembly Circuit testing Software testing Signal processing Flip-flops Logic Laboratories
Content Type	Text
Resource Type	Article

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