NDLI: Integrated Modeling, Generation and Optimization for Packet based NoC Topology

Content Provider	IEEE Xplore Digital Library
Author	Cai Jueping Liu Zheng Du Ming Li Zan Yao Lei
Copyright Year	2010
Abstract	In this paper, a methodology based on the cost of bus throughput, transmission latency and power consumption is proposed to achieve integrated optimization of NoC topology modeling and generation. The optimized framework’s static and dynamic properties ensure efficient core-to-core communication of the complete network. Our approach 1) fully exploits the regularity of standard topology and the flexibility of application-specific topology 2) generates a scalable network containing heterogeneous topologies, which raises the abstraction level of reuse from resources to subnets 3) satisfies NoC application. The performances of the topology are simulated and compared between the proposed methodology and regular NoC topologies, including mesh and optimal mesh architecture. Experimental results show the proposed design flow is efficient to provide better performance for predefined requirements, and minimal cost function is achieved. In addition, we applied several multimedia applications as case studies.
Starting Page	293
Ending Page	298
File Size	591484
Page Count	6
File Format	PDF
ISBN	9781424466955
ISSN	1550445X
e-ISBN	9781424466962
DOI	10.1109/AINA.2010.106
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-20
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Network topology Design methodology Throughput Delay Integrated circuit interconnections Power generation Optimization methods Cost function Design optimization Optimization NoC Topology modeling
Content Type	Text
Resource Type	Article

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