NDLI: A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems

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A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems

Content Provider	IEEE Xplore Digital Library
Author	Shan Tang Qiang Xu
Copyright Year	2008
Description	Author affiliation: Chinese Univ. of Hong Kong, Hong Kong (Shan Tang; Qiang Xu)
Abstract	Existing SoC debug techniques mainly target bus-based systems. They are not readily applicable to the emerging system that use network-on-chip (NoC) as on-chip communication scheme. In this paper, we present the detailed design of a novel debug probe (DP) inserted between the core under debug (CUD) and the NoC. With embedded configurable triggers, delay control and timestamping mechanism, the proposed DP is very effective for inter-core transaction analysis as well as controlling embedded cores' debug processes. Experimental results show the functionalities of the proposed DP and its area overhead.
Starting Page	416
Ending Page	421
File Size	240854
Page Count	6
File Format	PDF
ISBN	9781424419210
DOI	10.1109/ASPDAC.2008.4483986
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-21
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Probes Debugging Network-on-a-chip Monitoring System-on-a-chip Silicon Communication system control Hardware Design for disassembly Computer bugs
Content Type	Text
Resource Type	Article

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