NDLI: Soft error rate reduction using redundancy addition and removal

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Soft error rate reduction using redundancy addition and removal

Content Provider	IEEE Xplore Digital Library
Author	Kai-Chiang Wu Marculescu, D.
Copyright Year	2008
Description	Author affiliation: Carnegie Mellon Univ., Pittsburgh (Kai-Chiang Wu; Marculescu, D.)
Abstract	Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, circuit reliability has become more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. In this paper, we propose a novel framework based on redundancy addition and removal (RAR) for soft error rate (SER) reduction. Several metrics and constraints are introduced to guide our proposed framework towards SER reduction in an efficient manner. Experimental results show that up to 70% reduction in output failure probability can be achieved with relatively low area overhead.
Starting Page	559
Ending Page	564
File Size	187728
Page Count	6
File Format	PDF
ISBN	9781424419210
DOI	10.1109/ASPDAC.2008.4484014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-21
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error analysis Redundancy Sequential circuits Combinational circuits Logic circuits Circuit faults Degradation Flip-flops Delay Error correction codes
Content Type	Text
Resource Type	Article

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