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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Varadan, S. Wang, J. Jiang Hu |
| Copyright Year | 2008 |
| Description | Author affiliation: Texas A&M Univ., College Station (Varadan, S.) |
| Abstract | In nanometer regime, IC designs have to consider the impact of process variations, which is often indicated by manufacturing/parametric yield. This paper investigates a yield model - the probability that the values of multiple manufacturing/circuit parameters meet certain target. This model can be applied to predict CMP (chemical-mechanical planarization) yield. We focus on the difficult cases which have large number of partially correlated variations. In order to predict the yield for these difficult cases efficiently, we propose two techniques: (1) application of orthogonal principle component analysis (OPCA); (2) hierarchical adaptive quadrisection (HAQ). Systematic variations are also included in our model. Compared to previous work, the OPCA based method can reduce the error on yield estimation from 17.1%-21.1% to 1.3%-2.8% with 4.6x speedup. The HAQ technique can reduce the error to 4.1%-5.6% with 6x-9.4x speedup. |
| Starting Page | 543 |
| Ending Page | 548 |
| File Size | 272506 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424419210 |
| DOI | 10.1109/ASPDAC.2008.4484010 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-03-21 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random variables Semiconductor device modeling Planarization Predictive models Yield estimation Circuit synthesis Computational efficiency Manufacturing processes Virtual manufacturing Timing |
| Content Type | Text |
| Resource Type | Article |
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