NDLI: Hardware architecture design for explicit model predictive control

Content Provider	IEEE Xplore Digital Library
Author	Johansen, T.A. Jackson, W. Schreiber, R. Tondel, P.
Copyright Year	2006
Description	Author affiliation: Dept. of Eng. Cybern., Norwegian Univ. of Sci. & Technol., Trondheim (Johansen, T.A.)
Abstract	Solutions to constrained linear and hybrid model predictive control (MPC) can be explicitly characterized in terms of piecewise linear (PWL) state feedback control. A PWL controller is pre-computed using parametric programming, and the exact explicit MPC implementation corresponds to the evaluation of a PWL function in the control unit. It has recently been shown that such evaluation can be boosted by binary search tree data structures. We report digital hardware architecture design results for this type of PWL control, and show that explicit MPC solutions can be implemented in a standard field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) with about 20 kGates leading to computation times around one microsecond per evaluation for typical applications. This facilitates implementation of constrained MPC in small-scale industrial and consumer electronics applications that are characterized by fast sampling or low production cost, such as mechatronics, MEMS, rotating machinery, power electronics, and acoustics
Sponsorship	American Automatic Control Council IFAC
File Size	340360
File Format	PDF
ISBN	1424402093
e-ISBN	1424402107
DOI	10.1109/ACC.2006.1656501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	American Automatic Control Council(AACC)
Subject Keyword	Hardware Predictive models Predictive control Field programmable gate arrays Application specific integrated circuits Piecewise linear techniques State feedback Linear feedback control systems Functional programming Binary search trees
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in