NDLI: Enhanced Message Passing in Turbo Product Code

Content Provider	IEEE Xplore Digital Library
Author	Nan-Hsiung Yeh Steiner, P.L. Yan Li
Copyright Year	1965
Abstract	Turbo product code with single parity check (TPC/SPC) has demonstrated superior error correction capability over the conventional PRML channel. However, the performance usually suffers at higher code rate. A scheme to improve BER of TPC/SPC at higher code rate is proposed. By adding cyclic redundancy check (CRC) to TPC/SPC, a sub-block can be ensured error free after passing both the parity check and CRC. At the completion of each iteration, the messages from the error free sub-blocks are modified to greatly increase their confidence levels. The artificially high confidence level from those error free sub-block bits results in much more efficient iterations subsequently and greatly lowers the ultimate BER. It is found that enhanced message passing combined with noise prediction maximum likelihood (NPML) detection in the soft output Viterbi algorithm (SOVA) gives the best performance. Spinstand head/media signals passed through software channel are used to validate the channel performance.
Sponsorship	IEEE Magnetics Society
Starting Page	3769
Ending Page	3772
Page Count	4
File Size	156150
File Format	PDF
ISSN	00189464
Volume Number	44
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Message passing Product codes Parity check codes Cyclic redundancy check Bit error rate Iterative decoding Error correction codes Maximum likelihood detection Viterbi algorithm Maximum likelihood decoding Viterbi detection magnetic recording partial response signaling turbo codes
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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