NDLI: FPGA placement by graph isomorphism (abstract only)

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FPGA placement by graph isomorphism (abstract only)

Content Provider	ACM Digital Library
Author	Omidian Savarbaghi, Hossein Bazargan, Kia
Abstract	FPGA placement and routing are still challenging problems. Given the increased diversity of logic and routing resources on FPGA chips, it seems appropriate to tackle the placement problem as a mapping between the nodes and edges in a circuit graph to compatible resources in the architecture graph. We explore utilizing graph isomorphism algorithms to perform FPGA placement. We use a hierarchical approach in which the circuit and architecture graphs are simultaneously clustered to reduce the size of the search space, and then a novel reductive graph product method is used to solve the isomorphism problem. The graph product algorithm is called reductive as it eliminates a linear number of candidates at every step of the search process, reducing the number of candidate nodes by approximately 1/3. Compared to the annealing-based placement tool VPR 5.0, we achieve approximately 40% improvement in placement runtime, while improving the critical path delay by about 7% and wire length by 5%, while demanding 1.3% more channels on average.
Starting Page	284
Ending Page	284
Page Count	1
ISBN	9781450305549
DOI	10.1145/1950413.1950483
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Graph product Graph isomorphism Placement Clustering
Content Type	Text
Resource Type	Article

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