NDLI: A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

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A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

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A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

Content Provider	ACM Digital Library
Author	Shannon, Lesley Jamieson, Peter Gharibian, Farnaz
Abstract	Due to the rapid growth in the size of designs and Field Programmable Gate Arrays (FPGAs), CAD run-time has increased dramatically. Reducing FPGA design compilation times without degrading circuit performance is crucial. In this work, we describe a novel approach for incremental design flows that both identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach reduces placement run-time on average by more than 17% while typically maintaining the design's critical path delay and marginally increasing its minimum channel width and wire length on average. Instead of following the traditional approach of evaluating a circuit's pre-placement netlist, this new algorithm analyzes designs post-placement to detect proximity data. It uses this information to non-aggressively extract heterogeneous cluster groupings from the design, which we call "gems," that consist of two to seventeen clusters. We modified VPR's simulated annealing placement algorithm to use our Singularity Placer, which first crushes each cluster grouping into a "singularity," to be treated as a single cluster. We then run the annealer over this condensed circuit, followed by an expansion of the singularities, and a second annealing phase for the entire expanded circuit.
Starting Page	242
Ending Page	242
Page Count	1
ISBN	9781450326711
DOI	10.1145/2554688.2554726
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga Placement Cad Clustering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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Identifying and Placing Heterogeneously-sized Cluster Groupings Based on FPGA Placement Data

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

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Control signal aware slice-level window based legalization method for FPGA placement (abstract only)

A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

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