NDLI: High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)

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High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)

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High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)

Content Provider	ACM Digital Library
Author	van Haastregt, Sven Vissers, Kees Kienhuis, Bart Neuendorffer, Stephen
Abstract	During the 1990s, High Level Synthesis (HLS) slowly started emerging to allow designers to cope with the ever-increasing complexity of digital signal processing systems such as wireless receivers. Only recently, a new generation of high-quality commercial HLS tools capable of generating decent RTL architectures from algorithmic-style code has become available. Although these tools are now starting to be adopted for actual designs, detailed experiences and results for these tools in significant designs is still lacking. In this work we have analyzed the design process of a significant portion of a wireless communication application using AutoESL's AutoPilot HLS tool. We target a Xilinx Virtex-5 FPGA device and a clock frequency of 225 MHz. We have compared our HLS implementation to a reference implementation obtained using manual RTL design methods. We found that our HLS implementation is competitive to this reference implementation in terms of throughput and resource cost. The time needed to obtain a first HLS implementation matching throughput and resource cost aspects of the reference implementation is similar to the design time of the reference implementation. After obtaining a first HLS implementation, we were able to explore and implement different application architectures with HLS in only a couple of hours, thereby gaining significant savings in design time over manual RTL design, where architectural exploration may take weeks.
Starting Page	278
Ending Page	278
Page Count	1
ISBN	9781450305549
DOI	10.1145/1950413.1950468
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fpga High level synthesis Sphere decoder
Content Type	Text
Resource Type	Article

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