NDLI: Should the academic community launch an open-source FPGA device and tools effort?: evening panel

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The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop

Should the academic community launch an open-source FPGA device and tools effort?: evening panel

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

A 65nm flash-based FPGA fabric optimized for low cost and power

A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements

Scalable and deterministic timing-driven parallel placement for FPGAs

Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Memory-efficient and scalable virtual routers using FPGA

An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only)

A streaming FPGA implementation of a steerable filter for real-time applications (abstract only)

Microblaze: an application-independent fpga-based profiler (abstract only)

VEGAS: soft vector processor with scratchpad memory

Real-time high-definition stereo matching on FPGA

CoRAM: an in-fabric memory architecture for FPGA-based computing

Line-level incremental resynthesis techniques for FPGAs

Improved delay measurement method in FPGA based on transition probability

A monte-carlo floating-point unit for self-validating arithmetic

Reducing the pressure on routing resources of FPGAs with generic logic chains

FPGA side-channel receivers

Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only)

Using many-core architectural templates for FPGA-based computing (abstract only)

FPGA-based fine-grain parallel computing (abstract only)

Leap scratchpads: automatic memory and cache management for reconfigurable logic

Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array

Towards scalable FPGA CAD through architecture

Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder

An FPGA implementation of a sparse quadratic programming solver for constrained predictive control

Co-synthesis of FPGA-based application-specific floating point simd accelerators

Dealing with the "itanium effect" (abstract only)

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)

Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

NetTM: faster and easier synchronization for soft multicores via transactional memory

A platform for high level synthesis of memory-intensive image processing algorithms

Thermal and power characterization of field-programmable gate arrays

Performance estimation framework for automated exploration of CPU-accelerator architectures

Exploration of FPGA interconnect for the design of unconventional antennas

On timing yield improvement for FPGA designs using architectural symmetry (abstract only)

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only)

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

Improved double angle complex rotation QRD-RLS

DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research

An analytical model relating FPGA architecture parameters to routability

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)

Variation tolerant asynchronous FPGA (abstract only)

FPGA placement by graph isomorphism (abstract only)

Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs

Authenticated encryption for FPGA bitstreams

Bridging the GPGPU-FPGA efficiency gap

The RLOC is dead - long live the RLOC

Resolving implicit barrier synchronizations in FPGA HLS (abstract only)

Regular fabric for regular FPGA (abstract only)

Torc: towards an open-source tool flow

A prototype FPGA for subthreshold-optimized CMOS (abstract only)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only)

Fault modeling and characteristics of SRAM-based FPGAs (abstract only)

Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only)

BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only)

Should the academic community launch an open-source FPGA device and tools effort?: evening panel

Content Provider	ACM Digital Library
Author	Wawrzynek, John
Abstract	For years, many academic researchers in reconfigurable computing have been frustrated by their reliance on commercial FPGAs and tools. Commercial FPGAs have highly complex micro-architectures, come with undocumented binary interfaces, have no compatibility between generations, and come with difficult to use proprietary place and route tools. The FPGA vendors are making the right moves for serving their commercial customer base, but it seems at times these moves are in conflict with the needs of the academic research community. These problems make it difficult for academics to teach FPGA design and to participate in relevant research related to FPGAs. Complex FPGA fabrics and undocumented proprietary interfaces make it nearly impossible to build new tools to target actual commercial devices. University researchers are now hesitant to participate in FPGA architecture research because the level of complexity of FPGAs is beyond what is possible to implement in an academic setting. Reconfigurable computing application developers are at the mercy of complex FPGA devices and closed-source place and route tools - not optimized for computing applications. Some argue that the time is right for academia to break away and create an open source FPGA device. Such an effort would enable university researchers to take an active role in architecture design, and promote an open source community effort in developing and advancing the state of the art of tools. A similar situation existed in the early 80's surrounding processor design. As a result of competition among the big computer companies, microprocessor designs had evolved from very simple beginnings to highly complex architectures and equally complex compilers. Universities were largely on the sidelines, as they couldn't compete at the level of industrial designs of the day. "RISC" changed all that. By adopting simple architectures, universities were once again able to actually design and implement their own processors and to innovate with microarchitecture and compilers. Is it time for a "RISC" revolution for FPGAs? FPGA companies might argue that FPGA platforms are necessarily complex and out of the realm of what's possible to implement within an academic setting, and would say that an open source effort in not necessary, as they are helping to promote academic research by collaborations with universities, and donation of tools, and hardware platforms. This panel will discuss the pros and cons of an academic community led open FPGA device and tools development effort.
Starting Page	3
Ending Page	4
Page Count	2
File Format	PDF
ISBN	9781450305549
DOI	10.1145/1950413.1950417
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Dsp Fpga High level programming models Reconfigurable computing Signal processing Design tools Open source
Content Type	Text
Resource Type	Article

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