NDLI: Reducing the pressure on routing resources of FPGAs with generic logic chains

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Reducing the pressure on routing resources of FPGAs with generic logic chains

Content Provider	ACM Digital Library
Author	Zgheib, Grace Brisk, Philp Ienne, Paolo Parandeh-Afshar, Hadi
Abstract	Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than wires. To cope with these challenges, FPGA architects have divided wires into local and global categories and introduced fast dedicated carry chains between adjacent logic cells, which reduce routing resource usage for certain arithmetic circuits (primarily adders and subtractors). Inspired by the carry chains, we generalize the idea to connect lookup tables (LUTs) in adjacent logic cells. By exploiting the fracturable structure of LUTs in current FPGA generations, we increase the utilization of the existing LUTs in the logic cell by providing new inputs along the logic chain, but without increasing the I/O bandwidth from the programmable interconnect. This allows us to increase the logic density of the configurable logic cells while reducing demand for routing resources, as long as the mapping tools are able to exploit the logic chains. Our experiments using the combinational MCNC benchmarks and comparing against an Altera Stratix-III FPGA show that the introduction of logic chains reduce the average usage of local routing wires by 37%, with a 12% reduction in total wiring (local and global); this translates to improvements in dynamic power consumption of 18% in the routing network and 10% overall, while utilizing 4% fewer logic cells, on average.
Starting Page	237
Ending Page	246
Page Count	10
File Format	PDF
ISBN	9781450305549
DOI	10.1145/1950413.1950458
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Generic synthesis Dedicated connection Fpga Routing wire Logic chain
Content Type	Text
Resource Type	Article

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