NDLI: FPGA-based fine-grain parallel computing (abstract only)

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The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop

Should the academic community launch an open-source FPGA device and tools effort?: evening panel

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

A 65nm flash-based FPGA fabric optimized for low cost and power

A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements

Scalable and deterministic timing-driven parallel placement for FPGAs

Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Memory-efficient and scalable virtual routers using FPGA

An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only)

A streaming FPGA implementation of a steerable filter for real-time applications (abstract only)

Microblaze: an application-independent fpga-based profiler (abstract only)

VEGAS: soft vector processor with scratchpad memory

Real-time high-definition stereo matching on FPGA

CoRAM: an in-fabric memory architecture for FPGA-based computing

Line-level incremental resynthesis techniques for FPGAs

Improved delay measurement method in FPGA based on transition probability

A monte-carlo floating-point unit for self-validating arithmetic

Reducing the pressure on routing resources of FPGAs with generic logic chains

FPGA side-channel receivers

Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only)

Using many-core architectural templates for FPGA-based computing (abstract only)

FPGA-based fine-grain parallel computing (abstract only)

Leap scratchpads: automatic memory and cache management for reconfigurable logic

Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array

Towards scalable FPGA CAD through architecture

Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder

An FPGA implementation of a sparse quadratic programming solver for constrained predictive control

Co-synthesis of FPGA-based application-specific floating point simd accelerators

Dealing with the "itanium effect" (abstract only)

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)

Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

NetTM: faster and easier synchronization for soft multicores via transactional memory

A platform for high level synthesis of memory-intensive image processing algorithms

Thermal and power characterization of field-programmable gate arrays

Performance estimation framework for automated exploration of CPU-accelerator architectures

Exploration of FPGA interconnect for the design of unconventional antennas

On timing yield improvement for FPGA designs using architectural symmetry (abstract only)

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only)

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

Improved double angle complex rotation QRD-RLS

DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research

An analytical model relating FPGA architecture parameters to routability

High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)

Variation tolerant asynchronous FPGA (abstract only)

FPGA placement by graph isomorphism (abstract only)

Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs

Authenticated encryption for FPGA bitstreams

Bridging the GPGPU-FPGA efficiency gap

The RLOC is dead - long live the RLOC

Resolving implicit barrier synchronizations in FPGA HLS (abstract only)

Regular fabric for regular FPGA (abstract only)

Torc: towards an open-source tool flow

A prototype FPGA for subthreshold-optimized CMOS (abstract only)

FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only)

Fault modeling and characteristics of SRAM-based FPGAs (abstract only)

Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only)

BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only)

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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