NDLI: A 65nm flash-based FPGA fabric optimized for low cost and power

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A 65nm flash-based FPGA fabric optimized for low cost and power

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A 65nm flash-based FPGA fabric optimized for low cost and power

Content Provider	ACM Digital Library
Author	Pevzner, Val Kaptanoglu, Sinan Morosan, Mihai Landry, Joel Li, Fei Hecht, Volker Greene, Jonathan Feng, Wenyi Krouglyanskiy, Anton
Abstract	This paper describes a non-volatile reprogrammable FPGA fabric, whose configuration data are provided directly by flash memory. The fabric is optimized for low-cost, low-power applications, leveraging the density of flash and the elimination of conventional configuration SRAM and its attendant static power. After surveying the necessary background on flash and its application to FPGAs, the 1T flash cell is described along with relevant novel aspects of the fabric architecture. The addition of a third level of switching between inter-cluster signals and logic inputs helps to reduce area and raise typical utilization above 95%. Despite the longer signal path, performance is maintained by synergism between the improved routing flexibility and extreme minimization of the fastest LUT input delay. Test cost is reduced by built-in circuits that can test all switches without reprogramming the flash memory. The fabric has been implemented in a 65nm CMOS embedded flash process.
Starting Page	87
Ending Page	96
Page Count	10
File Format	PDF
ISBN	9781450305549
DOI	10.1145/1950413.1950434
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Iib Packing Flash memory Programmable routing Built-in self test Clos network Fpga architecture Input interconnection block
Content Type	Text
Resource Type	Article

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