NDLI: Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

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Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)

Content Provider	ACM Digital Library
Author	Paul, Somnath Bhunia, Swarup
Abstract	Conventional Field Programmable Gate Array (FPGA) architectures leverage on the purely spatial computing model where a design is realized in the form of a small multiple-input single-output lookup tables (LUTs) connected through programmable interconnect switches. However, such a model incorporates an elaborate programmable interconnect network which becomes a major performance bottleneck and leads to poor scalability across process technology nodes. In this paper we evaluate an alternative two-dimensional static random access memory (SRAM) array based reconfigurable computing fabric, referred to as "Memory Based Computing" (MBC) that departs from a purely spatial architecture by advocating multi-cycle evaluation at each computational element. Within a computational element, it uses a dense two-dimensional SRAM array to map large multi-input multi-output functions as LUT and evaluate them in time-multiplexed topological fashion. Multi-cycle execution at each computing node is accomplished using a local interconnect architecture. The proposed framework substantially reduces the requirement for global interconnects by folding computational resources onto a single computational element. We explore the design space for MBC to optimize the major design parameters and compare the performance, power dissipation and energy-delay product for benchmark applications between MBC and conventional SRAM-based FPGA. Simulation results show that compared to a clustered FPGA model, the proposed framework achieves 57% improvement in performance, 30% improvement in Energy Delay Product (EDP) and 10% improvement in technological scalability of performance for standard benchmark circuits. Finally, we validate the functionality of MBC framework and timing of different operations by mapping several small applications on a Cyclone III FPGA platform from Altera.
Starting Page	283
Ending Page	283
Page Count	1
ISBN	9781450305549
DOI	10.1145/1950413.1950481
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-02-27
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Memory based computation Field programmable gate array (fpga) Recongurable hardware
Content Type	Text
Resource Type	Article

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