NDLI: Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications

Content Provider	IET Digital Library
Author	Pal, Soumitra Gupta, Vivek Ki, Wing Hung Islam, Aminul
Abstract	Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.
Starting Page	584
Ending Page	595
Page Count	12
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 5, Aug (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5283
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-02-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	CMOS Integrated Circuit CMOS Memory Circuit Complementary Metal Oxide Semiconductor Model Computer Communication Conventional 6T SRAM Data Stability Deep-subthreshold Regime Electrical/electronic Equipment Energy Utilisation Internet of Things Leakage Current Low Power Electronics Memory Circuit Nanometre Technology Node Other Computer Network Power Consumption Power Dissipation Principal Design Metrics Read Decoupling Semiconductor Storage Size 16 Nm SRAM Cell SRAM Chips Static Random-access Memory Cell Transmission Gate-based 9T SRAM Variation Resilient Low Power Voltage Scaling
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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