NDLI: Single bit-line 11T SRAM cell for low power and improved stability

Content Provider	IET Digital Library
Author	Lorenzo, Rohit Pailly, Roy
Abstract	This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a row-based virtual ground signal to eliminate unnecessary bit-line discharge in the un-selected row, thus decreasing energy consumption. The cell also achieves low power due to the stack effect. To show the effectiveness of the cell, its design metrics are compared with other published SRAM cells, namely, conventional 6T, 10T, 9T, and power-gated 9T (PG9T). In standby mode, from 6.71 to 7.37% leakage power reduction is observed for this cell at an operating voltage of 1.2 V and 29.21 to 58.68% & 32.74 to 71.11% improvement for write & read power over other cells. The proposed cell exhibits higher write and reads static noise margins with an improvement of 13.54 and 63.28%, respectively, compared to conventional 6T SRAM cell. The cell provides write delay improvement from 29.77 to 49.40% and read delay improvement from 7 to 12% compared to 9T, 10T, and PG9T, respectively.
Starting Page	114
Ending Page	121
Page Count	8
ISSN	17518601
Volume Number	14
e-ISSN	1751861X
Issue Number	Issue 3, May (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/14/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2019.0234
Journal	IET Computers & Digital Techniques
Publisher Date	2020-02-05
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Bit-line Discharge Delay Improvement Digital Circuit Design, Modelling And Testing Electrical/electronic Equipment Energy Consumption Energy Utilisation Integrated Circuit Design Leakage Power Reduction Low Power Electronics Memory Circuit PG9T Power Gating Transistors Power-gated 9T Row Half Select Disturbance Row-based Virtual Ground Signal Semiconductor Storage Single Bit-line SRAM Cell SRAM Chips Stack Effect Static Noise Margins Static Random Access Memory Cell Transmission Gate Voltage 1.2 V Write-read Power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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