NDLI: Six-track multi-finger standard cell library design for near-threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

Content Provider	IET Digital Library
Author	Lim, Yang Wei Kamsani, Noor Ain Sidek, Roslina Mohd Hashim, Shaiful Jahari Rokhani, Fakhrul Zaman
Abstract	In this study, a six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi-finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place-and-route (P&R). The proposed library was analysed and compared with two eight-track multiplier layout libraries in the cell and block design level. Based on the place-and-route results of ISCAS'85 benchmark circuits, the proposed six-track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.
Starting Page	710
Ending Page	716
Page Count	7
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 5, Aug (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5542
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-03-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Automatic Place-and-route Based Width Unit Block Design Level Circuit Optimisation CMOS Integrated Circuit Complementary Metal Oxide Semiconductor Technology Design Area Digital Circuit Design Eight-track Multiplier Layout Libraries Energy Efficiency Integrated Circuit Layout Inverse Narrow Width Effect Layout Minimum Critical Path Delay Modelling And Testing Multifinger Layout Structure Multiplier Structure Library Near-threshold Operation Near-threshold Voltage Operation Parasitic Effect Performance Enhancement Semiconductor Integrated Circuit Design Six-track Multifinger Standard Cell Library Design Size 130 Nm
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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