NDLI: Compact and high-throughput parameterisable architectures for memory-based FFT algorithms

Content Provider	IET Digital Library
Author	Valencia, Daniel Alimohammad, Amirhossein
Abstract	Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.
Starting Page	696
Ending Page	703
Page Count	8
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 5, Aug (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5556
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-03-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application Specific Integrated Circuit ASIC Author Custom-developed Library Author Memory-based FFT Architectures Bit-true Simulation CMOS Integrated Circuit CMOS Logic Circuit CMOS Memory Circuit Combinatorial Mathematics Compact-throughput Parameterisable Architectures Computer Architecture Cycle-accurate Simulation Digital Arithmetic Method Digital Circuit Design, Modelling And Testing Discrete FFT Algorithm Discrete Fourier Transform Double-precision Floating-point Representation Fast Fourier Transform Fast Fourier Transform Algorithm Field Programmable Gate Array Fixed Point Arithmetic Fixed-point Representations Fixed-point Simulation Model Floating Point Arithmetic Hardware Description Languages High-throughput Parameterisable Architectures Integral Transforms in Numerical Analysis Integrated Circuit Design Logic And Switching Circuit Logic Circuit Logic Design Method Memory Architecture Memory Circuit Microprocessors And Microcomputer Mixed-radix Algorithm Numerical Operation Radix-2 Algorithm Radix-4 Algorithm Radix-8 Algorithm Reconfigurable Architectures Reconfigurable ReSource Regular Structure Semiconductor Storage Signal Flow Graph Size 45 Nm Split-radix Algorithm Standard CMOS Technology Storage Requirements Symmetries Property Synthesisable FFT Architectures Verilog Hardware Description Language Xilinx Virtex 7 FPGA
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

FFT Implementation with Fused Floating-Point Operations

Area efficient floating-point FFT butterfly architectures based on multi-operand adders

A Modified Split-Radix FFT With Fewer Arithmetic Operations

High-throughput and compact FFT architectures using the Good–Thomas and Winograd algorithms

Area and power efficient decimal carry-free adder

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors

Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor

Compact and high-throughput parameterisable architectures for memory-based FFT algorithms

Similar Documents

Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

FFT Implementation with Fused Floating-Point Operations

Area efficient floating-point FFT butterfly architectures based on multi-operand adders

A Modified Split-Radix FFT With Fewer Arithmetic Operations

High-throughput and compact FFT architectures using the Good–Thomas and Winograd algorithms

Area and power efficient decimal carry-free adder

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors

Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor

Compact and high-throughput parameterisable architectures for memory-based FFT algorithms