NDLI: High-performance DSP platform for digital hearing aid SoC with flexible noise estimation

Content Provider	IET Digital Library
Author	Kim, Sang Won Kim, Min Joon Kim, Jae Seok
Abstract	Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors’ DSP design is 2.71 mm2, and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library.
Starting Page	717
Ending Page	722
Page Count	6
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 5, Aug (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5374
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-03-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application-specific Instruction-set Processor ASIP Complex Hearing Aid Algorithm Digital Circuit Design, Modelling And Testing Digital Hearing Aid SoC Digital Hearing Aid System Digital Signal Processing Chips Flexible Electronics Flexible Noise Estimation Frequency 8.0 MHz Hardware Accelerators Hearing Aids Hearing Impairment High-performance Algorithm High-performance Digital Signal Processing Platform High-performance DSP Platform Instruction Sets Integrated Circuit Design Integrated Circuit Noise Layout Low Power Electronics Modelling And Testing Noise Environment Noise Estimation Algorithm Noise Handling Orthotics Power 1.3 MW Prosthetics Semiconductor Integrated Circuit Design Signal Processing And Detection Size 65 Nm System-on-chip Voltage 1 V
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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