NDLI: Low-power data encoding/decoding for energy-efficient static random access memory design

Content Provider	IET Digital Library
Author	Pasandi, Ghasem Mehrabi, Kolsoom Ebrahimi, Behzad Fakhraei, Sied Mehdi Kusha, Ali Afzali Pedram, Massoud
Abstract	This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a ‘0’ than a ‘1’ benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.
Starting Page	1152
Ending Page	1159
Page Count	8
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 8, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/8
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5564
Journal	IET Circuits, Devices & Systems
Publisher Date	2019-08-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	CMOS Integrated Circuit CMOS Memory Circuit Complementary Metal Oxide Semiconductor Technology Data Bit Reordering Algorithm Electrical/electronic Equipment Encoding Energy Consumption Energy Utilisation Energy-efficient Design Integrated Circuit Design Inverter Lenna Test Image Low Power Electronics Low-power Data Decoding Circuit Low-power Data Encoding-decoding Low-power Input Data Encoding Memory Circuit Multiplexers Power Consumption Semiconductor Storage SRAM Array SRAM Cell SRAM Chips Standard SRAM Static Random Access Memory Design Write Read Operation
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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