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Low-power adiabatic 9T static random access memory

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Low-power adiabatic 9T static random access memory

Content Provider	IET Digital Library
Author	Takahashi, Yasuhiro Nayan, Nazrul Anuar Sekine, Toshikazu Yokoyama, Michio
Abstract	In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses. The cell structure of the proposed SRAM has two high-value resistors based on a p-type metal-oxide semiconductor transistor, a cross-coupled n-type metal-oxide semiconductor (NMOS) pair and an NMOS switch to reduce the short-circuit current. The inclusion of a transmission-gate controlled by a write word line signal allows the proposed circuit to operate as an adiabatic SRAM during data writing. Simulation results show that the energy dissipation of the proposed SRAM is lower than that of a conventional adiabatic SRAM.
Starting Page	259
Ending Page	264
Page Count	6
Volume Number	2014
e-ISSN	20513305
Issue Number	Issue 6, Jun (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/joe/2014/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/joe.2014.0009
Journal	The Journal of Engineering
Publisher	The Institution of Engineering and Technology
Publisher Date	2014-04-28
Access Restriction	Open
Rights License	Creative Commons Attribution-No Derivs License (http://creativecommons.org/licenses/by-nd/3.0/)
Subject Keyword	Adiabatic Logic Principle Cell Structure Cross-coupled N-type Metal-oxide Semiconductor Data Writing Energy Dissipation Insulated Gate Field Effect Transistors Low Power Electronics Low-power Adiabatic 9T SRAM Low-power Adiabatic Static Random Access Memory Memory Circuit MOSFET NMOS Switch P-type Metal-oxide Semiconductor Transistor Semiconductor Storage Short-circuit Current SRAM Chips Trapezoidal-wave Pulses Write Word Line Signal
Content Type	Text
Resource Type	Article

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