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| Content Provider | IET Digital Library |
|---|---|
| Author | Jarrah, A. Jamali, M. |
| Abstract | Space-time adaptive processing algorithms have been proven to be a very effective way to mitigate the effects of multipath and interference. Due to the fast-changing clutter scenario, the stationary property of the data is destroyed and fails if the interference scenario ever becomes heterogeneous. Direct data domain (D3) methods can accommodate non-stationary data and can effectively suppress the clutter. However, the computation of D3 is very intensive. It is desirable to implement the D3 algorithm on a FPGA architecture for real-time applications. FPGAs can accommodate parallel and pipelined architecture. Here, the first FPGA design for the D3 algorithm and a new software package are presented. The software tool is capable of auto-generating a fully optimised VHDL representation of D3 and provides various performance parameters. The tool can be used by the designer to develop an overall system on chip (SoC) by using various constraints and options to meet certain performance criteria. Experimental results demonstrate that the authors' hardware version of the D3 algorithm can significantly outperform an equivalent software version. |
| Starting Page | 789 |
| Ending Page | 791 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 49 |
| e-ISSN | 1350911X |
| Issue Number | Issue 13, Jun (2013) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/13 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2013.1307 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | D3 Algorithm Data Stationary Property Digital Circuit Design, Modelling And Testing Digital Signal Processing Direct Data Domain Approach Electromagnetic Compatibility Electronic Engineering Computing Fast-changing Clutter Scenario Field Programmable Gate Array FPGA Design Fully Optimissed VHDL Representation Hardware Description Languages Interference Interference Scenario Interference Suppression Logic And Switching Circuit Logic Circuit Logic Design Method Signal Processing And Detection SoC Software Tool Space-time Adaptive Processing Space-time Adaptive Processing Algorithm System on Chip System-on-chip |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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