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Content Provider | IET Digital Library |
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Author | Guo, Jianping Ho, Marco Kwong, Ka Yee Leung, Ka Nang |
Abstract | A fast-transient capacitor-free low-dropout regulator (LDO) based on a flipped-voltage-follower (FVF) structure has been designed with the proposed digital detecting technique. By increasing the slewing at the gate of the power transistor through detecting the dynamic changes inside the circuit, load-transient recovery time can be decreased by 99.8%. The quiescent current of the proposed LDO is only 3.9 µA under normal operation. In addition, the circuit maintains a small chip area of 0.04 mm2 under 0.18 µm CMOS technology since no large RC components are needed to couple the output voltage spikes. |
Starting Page | 94 |
Ending Page | 96 |
Page Count | 3 |
ISSN | 00135194 |
Volume Number | 51 |
e-ISSN | 1350911X |
Issue Number | Issue 1, Jan (2015) |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/1 |
Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2014.3330 |
Journal | Electronics Letters |
Publisher Date | 2014-12-08 |
Access Restriction | Open |
Rights Holder | © The Institution of Engineering and Technology |
Subject Keyword | Amplifiers CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Technology Current 3.9 MuA DDT Digital Detecting Technique Flipped-voltage-follower Structure Load-transient Recovery Time Low-dropout Regulator Operational Amplifier Output Voltage Spikes Power Electronics Power Supply Power Transistor Power-area-efficient Transient-improved Capacitor-free FVF-LDO Size 0.18 Mum Supervisory Circuit Transient Analysis Voltage Regulators |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering |
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