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| Content Provider | IET Digital Library |
|---|---|
| Author | Reviriego, P. Maestro, J. A. |
| Abstract | Multiple way tables in which items can be placed on several buckets are used in many computing applications. Some examples are cache memories and multiple hash tables structures. In most cases, the items are stored in electronic memories that are prone to soft errors that can corrupt the stored items. To avoid data corruption, memories can be protected with a parity bit or with an error correction code. It is shown that most single bit errors can be detected in multiple way tables without adding a parity bit. This can be done by placing the items in a predetermined order in the multiple ways of the table. |
| Starting Page | 50 |
| Ending Page | 52 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 51 |
| e-ISSN | 1350911X |
| Issue Number | Issue 1, Jan (2015) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/51/1 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2014.3769 |
| Journal | Electronics Letters |
| Publisher Date | 2014-12-15 |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | Cache Memories Cache Storage Code Data Corruption Avoidance Efficient Error Detection Electronic Memory Error Correction Code Error Detection Code Memory Circuit Multiple Hash Table Structure Multiple Way Tables Parity Bit Radiation Effect (semiconductor Technology) Radiation Hardening (electronics) Semiconductor Storage Single Bit Error Soft Error |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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